1. Field of the Invention
The present invention relates to a semiconductor device and, in particular, to a semiconductor device using a thin film transistor (hereinafter referred to as a TFT).
2. Description of the Related Art
With a recent microminiaturization and high density arrangement of an SRAM, the current tendency has been from a high resistance load type heretofore employed toward a TFT load type SRAM. TFT as used for, for example, the TFT load type SRAM, etc., with a diffusion layer formed in a semiconductor substrate and used as the TFT gate will be explained below with reference to FIGS. 1(A) to 1(C).
As shown in FIG. 1(A), an element isolation area 102 is provided, by, for example, a selective oxidation method, at a predetermined area on the surface of, for example, a P type Si substrate 101. A gate oxide film 103, for example, is formed, by a thermal oxidation method, etc., on the resultant structure to have a thickness of about 10 nm. A polycrystalline silicon about 300 nm thick is deposited on the gate oxide film 103 and a predetermined pattern is formed by using a photoetching method to produce an ordinary MOSFET's gate electrode 104.
With the gate electrode 104 used as a mask, an As ion is implanted, for example, at a dose of about 5.times.10.sup.15 /cm.sup.2 and acceleration voltage of 35 KeV into the semiconductor structure to provide diffusion layers 105 for ordinary MOSFET's source and drain regions.
As shown in FIG. 1(B), a TFT gate oxide film 106 is then formed, by the chemical vapor deposition method, on the semiconductor structure at a thickness of about 20 nm. A polycrystalline silicon (hereinafter referred to as a TFT poly) for TFT channel and source and drain regions is deposited, by a CVD method, etc., on the resultant structure at a thickness of about 50 nm and a predetermined poly-Si pattern 108 is formed by the photoetching method as shown in FIG. 1(C).
Then, for example, an impurity ion is selectively implanted by a photoetching method in the source and drain formation areas of the polycrystalline silicon layer 108 to provide impurity regions, not shown. Thereafter, a predetermined metallization step etc., are performed to complete a semiconductor device.
Forming respective specific TFT gate and channel regions as a different structure from that shown in FIG. 1 will be explained below with reference to FIGS. 2(A) to 2(D).
First, an element isolation area 202 is formed by a selective oxidation method, etc., at a predetermined area on, for example, a P type silicon substrate 201 as shown in FIG. 2(A). A thermal oxidation film 203, for example, is formed on the semiconductor structure at a thickness of about 10 nm. A polycrystalline silicon is deposited on the resultant structure at a thickness of about 300 nm and a predetermined pattern is formed by the photoetching method to provide an ordinary MOSFET's gate electrode 204. With the gate electrode 204 used as a mask, an As ion is implanted in the semiconductor structure at a dose of about 5.times.10.sup.15 /cm.sup.2 and acceleration voltage of 35 KeV to provide diffusion layers 205 for normal MOSFET's source and drain regions.
As shown in FIG. 2(B), SiO.sub.2 is deposited by the CVD method, etc., on the semiconductor structure at a thickness of about 300 nm to provide an insulating interlayer 206. Then polycrystalline silicon is deposited by the same CVD method on the semiconductor structure at a thickness of, for example, about 100 nm. A predetermined pattern is formed by the photoetching method on the semiconductor structure to provide a TFT gate electrode 207.
As shown in FIG. 2(C), SiO.sub.2 is deposited by, for example, the chemical vapor deposition method on the semiconductor structure as shown in FIG. 2(C) to provide a gate oxide film 208.
A polycrystalline silicon (TFT poly) 209 for TFT channel and source and drain regions is deposited by, for example, the CVD method on the semiconductor structure at a thickness of about 50 nm.
As shown in FIG. 2(D), a predetermined poly-Si pattern 210 is formed by the photoetching method on the semiconductor structure. An impurity ion is, for example, selectively implanted by the photoetching method in the source and drain regions of the poly-Si pattern 210 to provide impurity regions, not shown. Thereafter, a predetermined metallization step etc., are performed to complete a semiconductor device.
In the TFT structure manufactured by the method as set out in conjunction with FIG. 1, if the distance between the TFT poly 108 and the gate electrode 104 of MOSFET over the silicon substrate 101 is decreased below 1 .mu.m at an area 109 shown in FIG. 1(C), TFT poly 108 to be essentially controlled by the diffusion layer 105 serving a both the TFT gate electrode and MOSFET drain is adversely affected by the MOSFET gate electrode 104 over the silicon substrate 101, failing to perform an essentially expected circuit operation.
For the distance of over 1 .mu.m, on the other hand, a major problem arises with those devices required of their microminiaturization. It is, therefore, not possible to lay out a very small SRAM cell using, for example, TFT.
In the TFT structure manufactured by the method of FIG. 2, as shown in FIG. 2(D), the area 109 is completely shielded by the TFT gate electrode 207 and, therefore, there occurs no problem as set out above.
However, the TFT structure requires its own special gate electrode 207, making the manufacturing steps more complicated. This makes a step layer formation tolerance stricter and, moreover, an overlying interconnection layer formation tolerance and its reliability stricter.